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Automated dispense systems for small substrate applications

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Many research laboratories and institutes use spin-coating technology to cost-effectively create thin-film coatings with precise thickness and uniformity control. In many cases, the most significant initial costs of development work are for the semiconductor-grade substrates. Consequently, many spin-on application projects may use irregularly shaped wafer pieces, microscope slides, and/or wafer die (1 cm × 1 cm) in early development work. Material deposition is typically performed with handheld syringes, manual pipettes, or more sophisticated digital repeater pipettes.

As process optimization begins to accelerate, the need to eliminate human variables becomes increasingly critical. Transferring the application method from a handheld dispense technique to a fixed mechanical nozzle with microprocessor control is a primary area of focus. Implementing automatic dispense options provides a feasible pathway; however, many variables must be considered when pursuing this option. An ideal solution combines the programmable control provided by an intelligent spin-coating (host) system with a disposable syringe barrel. This configuration is inherently capable of minimizing material consumption, mitigating cross-contamination, and providing precise programmable control.

auto dispensed used for spin coating

One such system is the disposable syringe dispense system (DSD-1), offered by Brewer Science. This system consists of a stainless steel/anodized aluminum housing with a proprietary design that features a mechanical roller suckback that ensures a positive clamp for drips and completely seals the nozzle tip from exposure to open air. This system provides extremely accurate, repeatable dispense rates and volumes. Each syringe accommodates various sizes of barrels and typically holds 30 cc or 55 cc of material. Various barrels are available, including transparently clear for general-purpose applications, light-sensitive amber, and opaque black (lightproof). Barrels also feature precision mated pistons that mitigate trapped air and enhance shot size uniformity. The DSD-1 system utilizes a proprietary flexible 16-gauge ID dispense luer tip and is compatible with viscosities up to 400 cP with a standard N2 or CDA pressure of 30 psi. With higher N2 pressures (to a maximum of 60 psi), the DSD-1 can support viscosities up to 13.5 kcP and dispense rates of 0.3 cc/s. The spin coater host software provides discrete control of the dispense timing to the nearest 0.1 second and combines with syringe pressure to control the dispense volume.

Auto Dispense used with spin coater

Syringe barrels are self contained, allowing users to interchange various process materials in a matter of seconds. The syringes are easily removable for filling and weighing and can be capped for storage over several days or weeks. The entire wetted assembly can be cleaned and reused and/or disposed of and replaced for the next chemical application. Inline Whatman™ Puradisc syringe filters are compatible with the syringe barrels and are available in a wide array of media types, pore sizes, and flow rates. They are simply inserted between the pressurized syringe barrel and the dispense tip. Common filter media types include Teflon®, polypropylene, nylon, and Kynar, and pore sizes include 0.05, 0.1, 0.2, 0.45, 1, 5, 10, and 25 µm. Optimal setup procedures include prewetting all PTFE Teflon® filters with solvent before plumbing on the process material. Prewetting will optimize the flow characteristics of the material through the filter and mitigate the risk of trapped air. The solvent purging process should be used in combination with opening the cartridge valve and purging any residual trapped air. Always invert the position of the filter to allow the output to flow from the top of the barrel.

Auto Dispense for Spin Coater

The DSD-1 dispense nozzle housing mounted in the lid of a Brewer Science® Cee® spin coater will accommodate multiple automated and/or manual syringe dispense options. A maximum of three other automated cartridges, pressure cans, syringes, or positive displacement or diaphragm pumps can be mounted simultaneously. With the Brewer Science® Cee® equipment user-friendly design, dispense recipes are easily entered, monitored, and stored through our stand-alone Windows®-based graphical user interface. Please refer to the Brewer Science® Cee® spin coating equipment landing page for additional information and detailed tool specifications.

Whatman™ is a trademark of GE Healthcare Companies. Teflon® is a registered trademark of E. I. du Pont de Nemours. Windows® is a registered trademark of Microsoft.

Process methodologies for temporary thin wafer handling solutions

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Use of temporary bonding/debonding as part of thin wafer handling processes is rapidly increasing. Users must determine which temporary bonding/debonding method is appropriate for a specific application. Some of the technologies that have been developed are chemical release, thermal slide separation, and ZoneBOND® debonding.

types of debonding

The chemical release process requires very little force to release the thinned device wafers from carriers and is recommended for low-volume, small-format, and compound semiconductor (CS) III-V materials.

The thermal slide debonding process is ideal for small-format applications with throughput requirements of 500-600 wafers (50-150 mm in diameter) per week and with thermal budgets up to 220°C.

The ZoneBOND® process is capable of separating large-format wafer pairs (with diameters of 200 mm or larger) containing large topography and/or perforations. It is also compatible with all wafer sizes, thicknesses, materials, and surface topographies.

Download the white paper to learn more about these three thin wafer handling process methodologies.

 

Thermal slide debonding for temporary bonding processes (Part 3 of 3)

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Thermal slide debonding represents the next significant advancement in obtaining high-yield thin wafer results. Initial detection of anomalies and cracks usually occurs during debonding; however, many causes for this damage originate during upstream bonding material coating, curing, bonding, and thinning processes. Moreover, only thermal separation tools that are highly precise and highly accurate will consistently render desirable process yields. The bonded pair is subjected to many thermal and compressive forces during processing and debonding. The thinned device layers are often very sensitive to outside factors including temperature, vacuum, and mechanical compression and release.

For debonding, relatively speaking, silicon materials are inherently more flexible than III-V compounds and allow greater control tolerances. Consequently compound semiconductor (CS) materials require significantly tighter control of platen temperature uniformity, pull force, vacuum fluctuations, platen separation, and platen co-planarity. The Cee® 1300CSX thermal slide debonder (see image below) has been specifically designed to meet and exceed these specifications.

 1300 CSX debonder

 

In this tool, wafer stacks are processed with the thinned device wafer orientated to contact the upper chuck and the carrier substrate is held in place by a vacuum emanating from the lower chuck. A manual insertion tool accurately aligns the bonded pair onto the lower platen lift pins. The lift pins are programmed electronically and provide precisely controlled acceleration for bringing the substrate to the desired set point temperature for heating the thermoplastic bonding material to the appropriate temperature to achieve a viscosity of <300 Pa·s. The following steps outline the standard process flow for thermal separation (see diagram below).

thermal slide

 

Operating the debonder involves the following processing steps:

  1. Load the debonding recipe (platen temperatures, pull force, thermal dwell times, electronic lift pin (ELP) positions, platen positional search windows, vacuum sensing threshold, etc.).
  2. Confirm the stack configuration (diameter and height/thickness). Recipes must match these physical characteristics.
  3. Using insertion tool, load the wafer onto the lift pins.
  4. Initiate the debonder recipe.
  5. The first recipe step is adjusting the lift pin positional height to allow a gradual increase in temperature for thermally sensitive materials.
  6. After achieving the appropriate thermal stabilization, the pre-bake step concludes, and the lower platen moves from the load to the press position.
  7. Upon reaching the press position, the platen is raised to the appropriate height to a predetermined vacuum search position.
  8. Once the minimum vacuum threshold is achieved, the system will enter the thermal stabilization step to ensure minimal temperature gradients.
  9. After the minimum temperature gradient is reached, the lower platen will pull in the x direction within preprogrammed force and speed limitations. During this pull, the following variables are monitored, controlled, and logged: z position, x position, force, speeds, upper and lower vacuum, upper and lower temperature, and process sampling time. The consistent profile of these variables is evidence of appropriate debonding parameters and may be used as a statistical process control.
  10. Upon debonding completion, the lower platen will drop and move to the load/unload position.
  11. The vacuum will shut off, and the lift pins will rise to the unload position for removal of the carrier.
  12. A specialized Gel-Pak® end effector is then inserted into tool under the upper platen and raised to a minimal distance (<2 mm) from the device wafer. Vacuum is released on the upper platen, and the wafer is gently transferred to the top surface of the Gel-Pak® end effector.

 

 thinned device

Transferring the intact device to a post-debonding spin-cleaning tool is the next critical step. The most common transfer method is outlined below:

 

  1. The device wafer and Gel-Pak® end effector are removed using the extraction tool assembly, and the entire Gel-Pak®/thinned device wafer structure is flipped onto a full sized porous ceramic spin chuck. Vacuum is applied through the spin chuck, and the device is released from the Gel-Pak® layer for cleaning.
  2. The remaining bonding material is removed from the device in a spin-cleaning process similar to a stream-puddle develop process. Megasonic cleaning is also a popular, safe method for cleaning residual bonding material to decrease cycle times and reduce solvent consumption (see photo below).
  3. After being cleaned, the device is lifted from the spin chuck with another clean Gel-Pak® carrier and mounted to a film frame on dicing tape.

 gel pak

megasonic cleaning

device wafer

 

Brewer Science is uniquely positioned to seamlessly integrate the materials, processes, and machines for adopting a precision temporary thermal bonding/debonding application. Our product portfolio includes high-temperature temporary bonding materials (WaferBOND® HT-10.10 material), precision spin coaters (Cee® 200X and 300X tools), bake plates (Cee®1300X and 200CBX tools), temporary bonders, debonders (Cee®1300DB and 1300CSX tools), thin-wafer transfer tooling, and cleaning tools (Cee®200XD, 300XD, and 300MXD tools). Please contact us today to learn more about these advanced technologies and products for overcoming daunting process challenges. We are standing by to assist you.

Gel-Pak® is a registered trademark of Gel-Pak LLC.

Thermal slide debonding for temporary bonding processes (Part 2 of 3)

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In addition to precisely controlling application of the materials that enable wafer bonding, a solvent-enriched sealed spin chamber contributes to process integrity. One of the most critical variables in achieving optimal uniformities at the desired target thickness is airflow dynamics. Ideal conditions are created in a sealed chamber with a prewet solvent nozzle, a backside rinse, a lid gasket, a splash ring (air-flow baffle), a programmable exhaust, and center-stream bonding material delivery. Radial and reverse-radial scanning dispense arms are not recommended because they require open bowl environments. Additionally, the scanning technique has not demonstrated significant advantages related to uniformity or material conservation.

A sealed bowl chamber (see bowl image below) improves material consumption, casting characteristics, and coating uniformity. A closed bowl environment combined with a programmable exhaust module allows the solvent vapor concentration to be precisely controlled at various stages in the spin-coating recipe.

programmable exhaust

Closed lid with programmable exhaust

Prewet dispense techniques deliver nominal amounts of base-solvent at the onset of depositing the bonding material. This dispense step serves the dual purpose of preparing the surface and increasing the initial bowl vapor concentration. Generally, exhaust is set at 0% (see solvent-enriched environment figure below) during the dynamic dispense and casting portions of the spin recipe. Exhaust flow is typically throttled to 50-100% (see open exhaust environment figure below) during the subsequent drying steps for adequate vapor removal.

solvent enriched environment

Solvent-enriched environment

open exhaust

Open exhaust environment

The lid gasket and splash rings seal the chamber and shape the exhaust flow for ideal edge coating. The gasket and rings also mitigate the risk of materials contacting the straight sidewall and redepositing on the upper device area of the substrate.

The backside rinse also helps prevent potential downstream bake plate, bonder, and debonder platen contamination by removing any residual bonding materials that collect on the rear side of the coated substrate.

Proper baking control is essential to achieve void-free media layers and overall high process yields for thick films. After the spin-coating/drying procedure, residual solvent will remain in the bonding material layer. Multistage bake cycles regulate the solvent evaporation rate and mitigate the risk of a “skinning effect.” Skinning results when the outer, exposed layers dry at a faster rate than lower, interior layers. Once skin forms, evaporating solvent below that skin can form blisters in the coating. This phenomenon can be observed if the film is not baked at multiple setpoints (120º-180ºC) and/or is too aggressively ramped to the respective baking temperatures.

During the backside processes (previously depicted in Part 1 figures) and in the thermal debonding process, failure to properly drive off residual vapors can also lead to vapor flash, greatly increasing the risk of device cracking. The use of two high-uniformity bake plates, featuring pneumatically controlled lift pins to permit proximity bake, soft contact bake, and hard contact bake methods (depicted in the figure below), are recommended for optimal curing results. Utilizing an initial proximity bake method with a nitrogen (N2) pillow lowers the risk of the substrate physically contacting the bake plate and receiving a thermal shock. The slower heating ramp also reduces the risk of blistering and cracking the outer, exposed film surface.

 

methods

N2 proximity, soft contact, and vacuum hard bake methods

A higher level of precision can be attained by using electronically controlled programmable lift pins. The electronic lift pins provide the user with specific proximity heights above the surface in any sequence or combination. In Brewer Science® Cee® bake plates, the heights are programmed in 0.001-inch increments, with an overall operating window from 0.001 inch through 0.750 inch (± 0.002 inch). This feature allows for more controlled temperature ramping and can emulate several bake plate temperatures with a single bake plate. This feature is also extremely valuable for safely handling thermomechanically sensitive materials, such as GaAs, InP, GaN, SiC, and sapphire substrates, because it reduces thermal shock.

lift pins

Thermocompressive bonding is often either overlooked or underestimated as a trivial step in the process flow. Precisely controlling process temperatures, achieving platen co-planarity, and maintaining the physical proximity gap between carrier and device during full evacuation (<5 mTorr) prior to physically joining the two substrates (see image below) are all critically important for successful thermocompressive bonding. Failure to control these parameters can lead to trapped pockets of air and solvent, which create voids. Scanning acoustic microscopes can reveal the existence and magnitude of such voids. These voids represent areas of non-uniform support during post-bonding backgrinding and could potentially cause adherence failure during backside processing and debonding processes. Close attention to the recipe parameters and carrier/device orientation is required to achieve a viable material bond line between wafers.

 

bonded wafers

 

Loading the bonding material–coated device in the lower stack position with the uncoated carrier immediately above is highly recommended. This loading position will reduce the risk of the bonding material making physical contact with the proximity separation pins during evacuation. Such contact could cause subsequent contamination of the next stack and also require excessive cleaning of the equipment.

Post-bonding thinning to thicknesses less than 100 µm requires the utmost in precision controls and programmability. Qualified vendors such as DISCO Corporation and Okamoto Corporation should perform this portion of the rough backside grinding process. Following the mechanical rough grinding procedure, post-thinning polishing is recommended to eliminate process-induced subsurface microcracks. SEM images clearly illustrate the presence of countless cleave planes resulting in non-uniform surface stress and warpage. A subsequent mechanical ultrafine grinding or chemical etching process can be used to remove this stress prior to additional thermomechanical processes.

backgrinding

Thermal slide debonding for temporary bonding processes (Part 1 of 3)

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The microelectronics industry is rapidly migrating to fabricating 3-D wafer stacking interconnects using through-silicon via (TSV) technology. Major market segments seeking to benefit from TSV technology include advanced packaging for memory/logic, light-emitting diodes (LEDs), and compound semiconductor (III-V) high-power radio-frequency (RF) devices. In this cutting-edge technology, fragile device substrates are bonded to carrier substrates with polymeric bonding materials for uniform support during backgrinding (thinning) processes. Device wafers containing various topographies, including etched topographies, high-aspect-ratio structures, trenches, and bored holes throughout the active component area, are first coated and planarized using spin-on bonding materials. Each coated device wafer is then mounted to a rigid carrier and thinned, usually to a thickness of less than100 µm, for further processing. The bonded pair, including the bonding material layer, will be subjected to a wide variety of thermo-mechanical stresses generated during backside processing to thin the device wafer and create electrical input/output redistribution layers (Figures 1 through 5). An effective temporary wafer bonding solution is expected to provide complete support, retain bond strength, and remain soluble for relatively low-temperature (>150°C) separation and cleaning. Temporary bonding process steps include the following:

  1. Coating the bonding material on device surfaces
  2. Baking the bonding material layer (by baking at temperatures of ≤180°C)
  3. Thermo-compressive bonding (at temperatures of ≤180°C)
  4. Mechanical and chemical backgrinding
  5. Post-thinning polishing to mitigate micro-crack propagation (also called stress relief etching)
  6. Photolithography (including baking at temperatures of ≤180°C)
  7. Plasma etching/reactive ion etching (RIE)
  8. Resist stripping
  9. Dielectric deposition (150°-220°C SiO2process)
  10. Seed layer deposition (by sputtering 220°C copper)
  11. Electroplating (nickel)
  12. Thermal debonding (at temperatures of 150°-190°C)
Tempory Bonding

 

During these process steps, the bonding material must remain adhered and provide sufficient support to the entire thinned device. To obtain consistently high process yields and throughputs, all upstream and downstream processes must be precisely controlled, often by very specialized equipment and tooling to achieve accurate and repeatable results. Coefficient of thermal expansion (CTE) mismatch poses a considerable threat to process integrity by inducing thermal stress. Using device and carrier materials with matching CTEs should be strongly considered. When the carrier and device CTEs cannot be matched, selecting materials with the closest possible CTEs will reduce risks associated with thermal stresses. Additionally, the carrier wafer retains greater structural integrity and will dominate the wafer bow effect. The thermoplastic bonding material layer provides a degree of compliance to relax this internal stress, and thicker bond lines (50-100 µm) work to amplify this effect.

Edge-trimming device wafers and/or using oversized carriers provides loading alignment tolerance and lessens the potential for knife-edge creation along the wafer’s edge, which creates a non-uniform radius and is the main source of chipping and subsequent crack propagation. Many issues related to this type of yield loss can be averted by using edge-prep techniques to replace the rounded edge with a straight wall. Removing 0.5-1.0 mm of the total diameter [of the device wafer?], depending on the overall wafer substrate size, is recommended.

describe the image

Brewer Science bonding materials are spin applied and require a precision spin coater with environmental chamber controls. Because of the relatively high viscosity of the bonding materials, standard (dip tube) pneumatic dispenses are not recommended for medium-volume, prototyping environments. Gravity-fed pneumatic reservoirs are viable for R&D and low-volume laboratory settings; however, manually pouring and/or transferring the material can result in the infusion of air, which creates microbubbles, and will detrimentally affect suck-back control. Thick-film bonding materials require significantly higher pressures to achieve nominal flow rates, and the overall pressure is directly proportional to the amount of gas dissolution. Recommended flow rates are >1 ml/s. Although bonding material volume will depend on the desired coating thickness, a good rule of thumb is to start with a minimum of 1.5 ml of bonding material per every 100 cm2 of coated surface area.

The ideal equipment for material delivery is a positive displacement pump system. These pumps have the significant advantage of not exposing the material to pressurized gas during fill, dispense, suck-back, and refill sequences. The pumps utilize stepper-motor-controlled diaphragms and provide optimal shot size, dispense rate, suck-back and refill accuracy. One top-of-the-line option, the Cybor 610 pump, provides a specialized recirculation feature to assist in outgassing during the initial purging operation. A reservoir system especially suited for high-viscosity materials is another beneficial accessory to mitigate the introduction of air bubbles during bottle-changing procedures. The system is installed upstream from a high-viscosity pump and features a capacitive sensor that monitors the liquid level and will auto-fill before air can reach the pump source line.

cybor

Cybor 610 and 5000 positive displacement pumps

Programmable bake plates and electronic proximity lift-pins

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 Since the dawn of the microelectronics industry, application engineers have required the ability to uniformly cure photosensitive materials. Particularly, curing wet-developable spin-applied films evenly across the substrate surface has presented a technical challenge. Such curing has become increasingly difficult with the introduction of large format substrates (200- to 300-mm) and the continual decrease in critical dimensions. Uniform baking across the substrate surface is critical to reduce over-curing, which causes "scumming," and under-baking, which causes undercut erosion and pattern collapse.

Cee Spincoater

High-uniformity precision bake plates have successfully achieved the level of performance needed to overcome these hurdles. These bake plates include features such as programmable bake times and multiple bake methods (contact, proximity, and vacuum) and are capable of maintaining temperature uniformity of ± 0.3% within the active working surface.

Multiple bake methods are performed with the use of a chuck having a series of concentric hole patterns that deliver either vacuum or nitrogen proximity gas. The concentric patterns determine the active size-specific (2 inches to > 200 mm) areas for N2 gas or vacuum distribution. These ports serve a dual function by supplying N2 for proximity baking and by floating the substrate into the active process position during the loading and unloading bake recipe sequences.

Graph1

N2 Proximity Contact: In this method, the substrate is floated on a self-leveling “pillow” of nitrogen at about 0.006-0.020 inch from the bake plate surface during baking. The gradual heating of the substrate reduces the blistering and cracking of films that sometimes results from the use of fast-drying solvents. This bake method can eliminate the need for two separate bake plates with similar temperature set points (within 10°C). Proximity baking with an N2 pillow mitigates the risks associated with physical contact between the substrate and the bake plate and has been adopted for many photomask and display processing applications. The N2 gas pillow accurately aligns the substrate against the vertical centering stop pins during the loading process.

Gravity Soft Contact: In this method, the substrate is held against the surface of the chuck by gravity. This style provides an intermediate method between hard vacuum contact and proximity bakes where a controlled multiple-step set point acceleration ramp is required. This style is very flexible and is compatible with any substrate size within the working surface area of the bake plate (1 inch from the surface plate perimeter).

Hard Vacuum Contact: This method is the most accurate baking method for bake plates and uses vacuum ports to ensure intimate contact between the substrate and the bake plate. This style ensures baking uniformity and minimizes warping and/or bowing of the substrate.

Additionally, a bake plate should maintain minimal variation from the temperature set point during loading and unloading of a substrate. This objective can be achieved by utilizing a large thermal mass in the bake plate surface. Although critically important to minimizing temperature variation, this large mass typically limits the speed of the set point acceleration. Multiple bake plates are generally utilized for spanning large ranges of set point temperatures.

Brewer Science® Cee® bake plates equipped with programmable ramping temperature controllers and compatible software can give a single bake plate the ability to ramp from low to high temperatures with precise soak times and up to ten incremental temperature step changes. This feature is limited to temperature increases up to about 50°C, and requires significant cooling times between bake recipes.

Brewer Science® Cee® bake plates incorporate a sophisticated technology that can address this handicap by utilizing program-controlled electronic lift-pins. This option utilizes accurate stepper motor control (±0.002 inch) that will drive the lift-pins to 100 specific proximity process heights above the baking surface in any sequence or combination. The heights are programmed in 0.001-inch increments, with an overall operating window from 0.001 inch through 0.750 inch. Traditionally, this technology was only available on million-dollar track equipment. Recently, this capability has been adapted to a compact benchtop version that is intended specifically for prototype-scale production. This flexible feature enables faster ramping acceleration/deceleration and emulates several bake plate temperatures simultaneously, while maintaining a high degree of bake uniformity. This feature is extremely valuable for the safe handling of thermomechanical shock-sensitive materials such as gallium arsenide, lithium niobate, indium phosphide, gallium nitride, silicon carbide, and sapphire substrates.

screen wafer bake plate

Brewer Science® Cee® equipment engineers have utilized the KLA-Tencor® SensArray measurement probe to measure, track, and record temperature conditions produced by Cee® bake plates. The engineers have meticulously performed these process trials and developed user-friendly temperature matrixes for a variety of common temperatures used for a soft bake (100°C), post-exposure bake (PEB), and post-develop hard bake (205°C) for final curing.

ProgrammableBakePlates4

The following chart represents a temperature matrix reflecting a surface temperature of 200°C, and incremental descent from 0.600 inch to hard vacuum contact in downward steps in increments of 0.100-0.020 inch. Each positional height is allowed to stabilize for a period of 300 seconds (5 minutes), and uniformity is recorded at these heights.

graph

By eliminating the need for multiple bake plates, this programmable system is a cost-effective option in a space-saving design. This configuration is ideal for performing multiple set points (dual stage), baking "from the inside out" for thick-film materials such as MicroChem SU-8 materials, MicroChem KMPR® materials, Shipley BPR™-100 photoresist, and Brewer Science® WaferBOND® HT-10.10 materials, and mitigating concerns associated with the "skinning" effect.

The Brewer Science® Cee® high-uniformity bake plate product family brings together all these capabilities in a compact footprint designed for a lab-scale environment. Click here to learn more.

Developer options for spin-on photosensitive materials

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Developing photosensitive film layers to produce features of targeted sizes is a critical process step within any photolithography application. Application engineers have created several processes for performing this step with tank immersion (that is, a bath) and/or several adaptations of spin developing a single wafer to make patterns of features based on film areas of differing solubility. The use of immersion tank processes has steadily declined in MEMS fabrication and advanced lithography over the past decade due to excessive material consumption, non-uniform resolution, and poor clearing from high-aspect-ratio features due to insufficient agitation. Additionally, increased throughput requirements and smaller critical dimensions (CDs) have further shifted mainstream applications to single-wafer (track) spray/puddle process flows. 

 

The standard developer materials consist of low-concentration (< 3%) bases and acids (TMAH, KOH, lactic acid in aqueous solutions). Other popular solvent-based photoresists, dry films, and polyamides are typically resolved and rinsed with polar solvents including propylene glycol monomethyl ether acetate (PGMEA), propylene glycol monomethyl ether (PGME), acetone, and isopropanol (IPA).

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The most common single-wafer process is designed to deposit the developer solution onto the center of the wafer surface through a stream puddle technique. The wafer is then spun at low speed (0-50 rpm). The rotation is then stopped and held at 0 rpm to enable the material to “puddle” and allow the chemical reaction to actively dissolve the soluble areas of the patterned film. This process is very popular for thin films ≤ 1 μm thick and/or for small wafer applications. For thick films and/or high-aspect-ratio features, the stream puddle step may be repeated over several iterations to reapply fresh developer. However, because this method of development is inherently non-uniform, it can be problematic for many thick-film and large-surface-area processes. Often features along the wafer perimeter are underdeveloped, and center features are often over-exposed.

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The use of side-angle spray nozzles significantly enhances fluid deposition uniformity. The standard configuration utilizes two side-spray, V-line spray nozzles to evenly apply developer solution and deionized (DI) water across the substrate simultaneously. Some configurations use an open UHMW polyethylene lid with spray nozzles mounted either outside the wafer plane, spraying inward from the center of the wafer out (puddle spray), or directly over the substrate for continuous (direct) spray applications. The side spray nozzles are factory positioned outside the wafer plane (side orientation) and ensure uniform deposition for all substrate sizes (2-8 inches). The spray nozzles can also be used in a puddle developer application by quickly applying material to the substrate at a slow speed and then reducing the substrate speed to 0 rpm. Programming and setup options will also enable continuous-spray applications with the omission of all static (0 rpm) steps during the recipe and spray continuously throughout processing steps.

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Many of the latest specialized lift-off resists and dry films (MicroChem LOR and SU-8 resists and Shipley BPR™-100 resist) are not compatible with spray/stream puddle development and require immersion, continuous direct-angle spray, and/or megasonic-assisted processes. Immersion methods are less than ideal and are not preferable for the reasons mentioned above. Direct-angle nozzles are often used for continuous-spray applications and allow accelerated development of thick films (5-100 μm) with features having high aspect ratios. The direct angle provides sufficient agitation to penetrate the film and remove soluble material. Another distinct advantage of this method is the continuous replenishment of fresh solution to accelerate development.

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Introduction of megasonic development was a dramatic technology leap in this area. This development/cleaning technology combines a ProSys MegPie megasonic transducer with spray/stream developer systems. The radial megasonic array is specifically designed to apply uniform acoustic energy across the entire surface of the spinning substrate and gently lift away soluble materials without damaging fragile structures. This technology is uniquely suited to resolve extremely small CDs with high-aspect-ratio (> 5:1) structures for MEMS fabrication and advanced lithography (193- and 248-nm).

 

The Brewer Science® Cee® equipment line has been specifically engineered to accommodate all spin-developer process techniques including stream, spray, direct-angle, and megasonic-enhanced. As the predominant lab-scale equipment supplier for advanced R&D and prototyping, the Brewer Science® Cee® product team is eager to meet your specific application needs.

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Automated dispense systems for applying high-viscosity materials

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Process Engineers have explored several techniques for consistently dispensing high-viscosity resins for spin-on material applications. Manually pouring and/or using pre-filled syringes requires significant material consumption and excessive time and introduces microbubbles into the viscous material. Achieving consistently accurate dispense rates and volumes and controlled suck-back is a daunting challenge. Automatic dispense options provide a feasible solution, however, many variables must be considered when pursuing this option.

 

One cost-effective solution involves using a combination of gravity-fed pressurized cartridges (12-ounce capacity) and stainless steel reservoir cans (1-gallon capacity). This medium-volume option features disposable polypropylene liners within the transparent cartridge housing, which allow users to switch materials in a matter of seconds without risk of cross-contamination. Each entire chemically exposed liner can be cleaned and reused or disposed of and replaced for the next chemical application. Precision pneumatic dispense valves are triggered by host spin coaters and provide accurate shot size and suck-back operation. The host software provides discrete control of the valve timing to the nearest 0.1 second. Other flow-rate variables include the N2 or clean dry air (CDA) pressure to the reservoir and the volume control adjustment on the dispense valve near the point of use. 

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   This option provides significant improvements over manual techniques in delivering viscous materials to the substrate surface. However, all pneumatically pressurized reservoirs are prone to allowing dissolution of gases into the process material. This phenomenon varies depending on the material solubility to the pressurized gas (N2) and the flow characteristics and/or viscosity. Thick-film materials require significantly higher pressures to achieve nominal flow rates, and the overall pressure is directly proportional to the amount of dissolution. This trapped gas can result in anomalies in the coated film and inhibit control of the suck-back function, resulting in problematic drips. While this option is feasible for initial small-scale proof-of-concept and development laboratories, it is not ideal for medium-volume prototyping and pilot-line environments.

In direct contrast to pressurized reservoirs, positive displacement pumps (such as the Cybor 5000-610) do not directly pressurize the material during dispense operations or subsequent recharging. Also, many positive displacement pumps feature a recirculating system to facilitate a specific outgassing procedure when the material is being initially purged or not in continuous use. The Cybor 5000-610 intelligent dispense pump is considered the industry-standard positive displacement pump for dispensing high-viscosity thick-film resists and polyimides (≤ 50,000 cP). The Cybor 5000-610 pump delivers extremely accurate shot size, volume, and suck-back control as well as microbubble-free operation. This pump is controlled through a Windows®-based PC. The software is fully compatible with today’s automated wafer-processing cluster and track systems.

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Unfortunately, many R&D laboratories simply cannot justify the purchase of million-dollar track systems that would be compatible with the positive displacement pump solution. Furthermore, the vast majority of laboratory-scale, entry-level spin coaters are not PC-based and will not support the software necessary to interface with this solution.

All Brewer Science® Cee® spin coaters include PC-based controllers capable of hosting the IDI/Cybor ChemNet® software. Visit the Cee® spin coaters page to learn more.

 

Bake plate enhancements for optimal thick-film curing results

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High-uniformity bake plates have been displacing convection ovens for well over two decades in the microelectronics industry. The disadvantages of variable temperature zones, lengthened cure times, and considerable particle contamination have been thoroughly analyzed and confirmed. Although temperature uniformity remains the primary advantage for precision hot plates, virtually eliminating skinning effects for thin-film (< 1-5 µm) applications has been equally beneficial. The skin effect is well understood when baking “from the outside in” and is typical of baking in a conventional oven. This phenomenon is more pronounced with thick-film materials such as SU-8 photoresist, KMPR photoresist, BPR-100 photoresist, and WaferBOND® HT-10.10 material, which are very prone to the skin effect. This effect occurs when the outer exposed layer of the film dries and forms a skin before all of the solvents in the lower layers have evaporated. These process anomalies are often observed with today’s bake plates if the heating accelerations are too aggressive and/or the bake temperature or time is below recommended levels. Often the result is post-bake blistering and/or cracking, which renders the film unusable for downstream processing.

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To combat this issue, customers have deployed the use of multiple high-uniformity bake plates with multiple set points (dual stage) for performing a soft bake, post-exposure bake, and post-develop hard bake for final curing. However, the multi-plate option fails to provide a repeatable method for ramping up from ambient temperature to the set point and over-utilizes precious clean room or laboratory working surfaces. One potential solution to this problem is instituting programmable plates with multiple bake method options (proximity, gravity, and hard contact).

Proximity baking essentially floats the substrates on a “pillow” of inert gas that is blown through orifices in the chuck surface. A combination of heated gas, radiant heat from the chuck, and reflective radiant heat from the hood baffle uniformly heats the substrate. This slower heating of the substrate reduces blistering and cracking of films made from materials containing fast-drying solvents. Proximity baking can eliminate the need for two independent bake plates if the set points are relatively close (± 10°C). Proximity baking with an N2 pillow mitigates the risk of physical contact between the substrate and the hot plate and has been adopted for many photomask and display processing applications.

In a “soft-contact” bake, gravity alone holds the substrate to the surface of the chuck. This method is typically utilized as an intermediate option between a “hard contact” bake and a proximity bake, for multiple step warm-up.

In a “hard contact” bake, the substrate is held to the surface by applying a vacuum to the underside of the substrate. This method ensures baking uniformity and minimizes bowing and warping of the substrate.  


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The latest process enhancement combines the existing bake methods (proximity, soft contact, or hard contact) with programmable lift pins. The electronic lift pins are used for automated loading and unloading of the process wafers and provide enhanced repeatability. Furthermore, they have been designed for maximum flexibility and will accommodate all standard and semistandard sizes from 2 inches (with proper placement of the flat) through 200 mm. The electronic lift pins provide the user with 100 specific proximity process steps above the surface in any sequence or combination. The heights are programmed in 0.001-inch increments with an overall operating window from 0.001 inch through 0.750 inch (± 0.002 inch). In many scenarios, this feature allows for faster ramping acceleration/deceleration and emulates several bake plates temperatures simultaneously. This feature is also extremely valuable for safe handling of thermomechanically sensitive materials such as GaAs, LiNbO3, InP, GaN, SiC, and sapphire substrates. The Brewer Science® Cee® line of high-uniformity bake plates are the only ones to bring together all referenced capabilities in a compact footprint designed for a lab-scale environment. See the Cee® bake plate web page for additional information and detailed tool specifications.

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Processing wafers with high-topography 3-D structures

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43-µm deep pillars with oxide hard mask remainingExtreme trench fillingVia filling

Over the past decade, Brewer Science has developed and published various methods of creating a planar surface over three-dimensional (3-D) structures. Sharing these results invariably leads to a potential customer asking, “Can you fill the holes in my substrate that are x in size?” The short answer to the question is “Yes, we can.” Filling holes, however, is rarely the only thing customers want to do. Typically they want to do something else, for instance, coat a photoresist, maintain chuck vacuum, support a structure, etc. That “something else” usually presents a challenge that is very different than just filling holes. For Brewer Science to provide the best solution for your particular structure and need, our highly experienced engineers and scientists must ask many more questions about what processes are acceptable and what downstream conditions the substrate must withstand.

To minimize cost and complexity, we offer process and material flexibility and compatibility with a standard photolithography track. We provide materials to level 3-D topography using the following methods:

Dry etch back

  • Requires an etching tool and bay transfer
  • Includes a variety of processes for which Brewer Science coatings are highly effective

Expose and develop

  • Requires an exposure tool and a developer spin bowl
  • Removes with dry etching
  • Takes advantage of the very good chemical resistance offered by Brewer Science materials

Wet etch back

  • Uses TMAH or solvent developer
  • Requires a developer spin bowl
  • Offers processing with no bay

Jim Lamb at Science Cafe

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James Lamb Photo resized 600

At the Science Café event held at Farmers Gastropub on April 19, James E. (Jim) Lamb III, Brewer Science Corporate Technology Strategist and Director of the Printed Electronics Technology Center, spoke to the Springfield, MO, community about printed electronics and what we can expect to see in the future. His interesting and informative presentation described some of the most advanced applications that will enhance people’s lives.  Science Café, sponsored by the Discovery Center and the Jordan Valley Innovation Center, provides the community with the opportunity to learn more about science and engage in interesting discussions in a casual environment. 

 

 

Background of multilayer processing

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As semiconductor devices evolve, smaller and smaller feature sizes are required to achieve the performance desired by the consumer. Smaller features give rise to lower power consumption for mobile devices, less expensive devices due to the ability to manufacture more chips per wafer, and faster overall speed. 

Why multilayer?

Smaller feature sizes also lead to higher aspect ratios in the photoresist, which cause pattern collapse and result in smaller processing windows. Therefore, photoresists have become thinner to offer higher resolution and to overcome pattern collapse. Typical photoresist thicknesses for today’s cutting-edge immersion processing are in the range of 60 nm to 100 nm, whereas typical photoresist thicknesses just a few years ago were about 150 nm. The trade-off for using thinner photoresists is a smaller etch budget for pattern transfer into the substrate. For this reason, multilayer patterning is needed.

How multilayer patterning works

Current multilayer patterning uses a thin photoresist with a thin inorganic or organometallic etch barrier layer (a hardmask, HM) that is deposited by either chemical vapor deposition (CVD) or spin-coating processes over the top of a thicker layer that is high in carbon content (a carbon hardmask, CHM). Some examples of CVD hardmask layers include SiON, SiN, and TiN. Organosilicates are one example of a spin-on hardmask. An example of a carbon hardmask applied by CVD is alpha-carbon. Spin-on carbon (SOC) hardmask layers consist of organic polymer solutions that are high in carbon content by design.

High inorganic content in the hardmask layer is important for transferring the photoresist image through the multilayer stack. High inorganic content allows for faster plasma etching in a fluorinated etch gas, thus reducing the photoresist thickness required to pattern the hardmask.  High inorganic content also slows the hardmask etch rate in oxygen plasma so that the hard mask maintains its integrity while transferring the photoresist pattern into the carbon hardmask layer.

High carbon content in the carbon hardmask layer is important because carbon etches slowly in the plasma gases typically used to etch into inorganic substrates such as silicon, polysilicon, SiO2, and low-k dielectrics.

Multilayer processing with spin-on coatings is a simpler process than CVD multilayer processing. The entire multilayer stack is applied in the coating module of a track, which eliminates the need to transfer wafers to another module for deposition.

OptiStack® multilayer systems

Brewer Science® OptiStack® systems simplify the overall lithography process by offering a universal lithography platform that eliminates topography dispersion and maintains optimal optical interfaces in the same focal plane, regardless of the substrate optical properties.

High aspect ratio features created with multilayer process

OptiStack® HM710 material on OptiStack® SOC110D material. High etch selectivity permits very thin hard mask and straight profiles.

View OptiStack® systems customer advantages

Solvent vapor control for optimal thick-film spin coating

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One of the most critical variables in spin-coating processes is coating uniformity. In many cases, engineers are challenged with achieving ultralow total thickness variation at high film thicknesses while conserving expensive materials. To achieve such a highly uniform coating, automated control of the solvent vapors is essential. A closed bowl environment combined with a programmable exhaust module allows the solvent vapor concentration to be precisely controlled at various stages in the spin-coating process.

Creating a solvent-rich environment: Prewet dispense step

Typically, creating a solvent-rich environment is optimal for the initial dynamic dispense. This step is often accomplished through a prewet dispense step that is performed immediately before thick-film deposition. The step consists of dispensing a small volume of solvent onto the substrate surface, which quickly casts the solvent onto the interior bowl surfaces. This preparation has the dual benefits of increasing vapor enrichment in the spin chamber and prepping the surface of the substrate for optimal spreading characteristics. The spin chamber exhaust is typically programmed to 0% flow during this phase, which mitigates the risk of solvent evaporation prior to the dispense step.

Programmable exhaust at 0% creating a solvent-rich environment

Applying the material: Dynamic dispense step

The next phase, the dynamic dispense step, uniformly spreads the coating material across the wafer surface. The material is applied while the substrate is spinning at relatively low speeds of 200 to 500 rpm. The dynamic method enables optimal coverage of the surface area while minimizing the overall volume of wasted material. In many cases, viscous materials for thick-film applications will be delivered through a positive displacement pump and will have maximum shot sizes of 16 to 20 ml of total volume. Following the deposition step, the spin speed is slowly ramped to establish the final thickness. The programmable exhaust control plays a significant role in determining the speed required for the desired thickness. Depending on the material composition, molecular weight, and viscosity, the exhaust is generally throttled at 0% to 50% closed. The combined effects of spin speed, vapor concentration, and time will determine the final coating thickness.

Stabilizing the film: Drying step

Typically, the casting process is followed with a longer drying step to remove residual solvents and increase the physical stability of the film. Thin-film applications often utilize a higher spin speed for this effect; however, many thick films must remain at the casting speed and/or slow to a lower speed to prevent additional thinning. We recommend the programmable exhaust be set at 100% during this phase to assist in faster solvent evaporation. This setting provides the additional benefit of removing the residual vapors from the chamber before the tool operator opens the lid at the conclusion of the process.

Exhaust flow at 100%

Spin speed, acceleration (centrifugal) force, and drying rate are the most important variables in determining the final film thickness and uniformity. Brewer Science® Cee® products provide these precision controls to enable optimal coating results for lab-scale and pilot-line applications.

Cee 200CBX shown with optional programmable exhaust

Cee® 200CBX shown with optional programmable exhaust module.

Etch protection questions and answers

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One of our recent articles discussed the creation of through-silicon vias using ProTEK® PSB photosensitive etch protection material. In this post, we will follow up by addressing a few of the frequently asked questions regarding our etch protection materials.

What etchants can these materials withstand?

Three classes of Brewer Science® ProTEK® materials are available to provide protection against alkaline and acid etchants as well as Bosch deep reactive ion etching (DRIE) processes. ProTEK® B3 and ProTEK® PSB coatings are designed to protect against alkaline etchants. ProTEK® A3 and ProTEK® PSA materials are designed to protect against acid etchants. ProTEK® SR scratch-resistant coating resists the etch gases used in the Bosch DRIE process.

ALKALINE: ProTEK® B3 and ProTEK® PSB coatings withstand KOH, TMAH, NaOH, and NH4OH at elevated temperatures as well as some acids such as hydrochloric, sulfuric, and phosphoric acids and buffered oxide etchant (BOE) at room temperature.

ACID: BSI.P09047 and BSI.P09022 coatings are resistant to acid etchants such as nitric, liquid hydrofluoric, acetic, and hydrochloric acids as well as BOE and HNA (which is HF, HNO3, and acetic acid in a ratio of 1:2:3.2). While these materials are also resistant to alkaline solutions, they may lose adhesion to the wafer during alkaline etching.

OTHER: ProTEK® SR material is resistant to some acid etchants such as hydrochloric, sulfuric, and phosphoric acids and BOE at room temperature. It is also resistant to the fluorinated etch gases used in the Bosch DRIE process such as SF6 and C4F8.

Do these materials require a primer?

Whether or not a primer is required to use ProTEK® coatings depends on the process. Coatings used during a long alkaline etch must have a primer. Without a primer, the coatings would eventually peel off the substrate during etching. The other materials do not typically need a primer, but the need for a primer does depend on the specific application.

For applications in which a wafer is coated with an acid-resistant coating and a short alkaline etch is needed before the acid etch, a primer is not normally needed. The necessity for a primer will depend on how short the alkaline exposure is and how aggressive the etch is in terms of bath temperature and concentration.

A primer is required if BSI.P09022 coating will be used as an etch mask for liquid HF etching of glass. A single primer for this application has not yet been named, but customers have demonstrated success using a chrome-nickel or chrome-gold seed layer.

How thick must these films be to resist the wet etchant?

A thick film is not required for alkaline etch protection. As long as a continuous film is applied, an alkaline etch solution will not penetrate the coating. However, a thicker coating may be required when working with acids. The thickness will be determined by the etchant, the etchant concentration, and the etch time.

Visit our MEMS FAQs page for answers to other commonly asked questions.

Photosensitive etch mask for creating through-silicon vias (TSVs)

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Through-silicon vias (TSVs) are becoming increasingly common for high-speed and high-bandwidth connections on a chip. TSVs are especially important in 3D packaging schemes and are also used in many sensor, MEMS, and LED devices.

While it is common to use deep reactive ion etching (DRIE) for creating the TSVs, wet etching of the silicon to create vias is a cost-effective process. In contrast to DRIE’s single-wafer processing that uses more expensive plasma etching equipment, wet-etch TSV formation allows batch processing using relatively inexpensive equipment (wet processing baths).

Etch mask challenges

One of the main challenges in wet etching of silicon is availability of a cost-effective etch mask scheme for protection during etching.

Conventional schemes for etch masks include chemical-vapor-deposited (CVD) silicon nitride (SiN) or silicon dioxide–based etch masks. The mask process involves several steps including specialized tools for high temperature CVD processing and dry-etch processing apart from the use of standard photolithography tools. The masking process and required toolset effectively raise the cost of ownership (CoO) of a wet-etch process, which would otherwise be a cost-effective option for users.

Brewer Science presents an elegant spin-on etch mask solution that minimizes the number of steps used for creating an etch mask and avoids the use of CVD-based tools for etch mask creation. The etch mask offers complete protection without pin-holes or delamination during silicon etching using alkaline etch baths (potassium hydroxide [KOH] or tetramethyl ammonium hydroxide [TMAH]).

Figure 1

Figure 1. Comparison of etch mask process scheme for wet-etch protection using (a) silicon nitride mask and (b) ProTEK® PSB spin-coatable etch mask

Cost-effective TSV creation

We have created TSVs using ProTEK® PSB photosensitive material for etch protection. The process provides good control and etch pattern integrity that is suitable for commercial production of TSV wafers for advanced interconnect structures.

Figure 2

Figure 2. SEM images showing TSVs of various dimensions created using ProTEK® PSB coating as an etch mask

Brewer Science® ProTEK® materials can protect entire surfaces and serve as effective etch masks for creating TSVs and other microstructures on silicon using wet etching. ProTEK® products provide a low-CoO option compared to conventional CVD-based etch mask techniques. As wafers become thinner, wet-etch TSV formation becomes more viable, providing a low-cost option to device manufacturers.

Thin-wafer handling: Spin chuck designs for thinned substrates

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Thin-wafer processing trends

Several spin-coating process applications require the ability to uniformly coat, develop, and/or rinse (clean) thinned and fragile substrates. Safely handling these fragile materials is paramount and requires specially designed spin chucks and thin-wafer handling techniques. The substrates are made of a wide array of materials, and some of the more popular ones include flexible polymer films (for example, fluorinated ethylene propylene [FEP] and polyester [PET]) and metal foils (titanium, aluminum, and steel). These materials are common for markets within the optics, thin-film transistor (TFT) display, and photovoltaic (PV) industries. Thicknesses of the substrates often range from 50 to 100 µm (0.001 to 0.004 inch) and are cut into various shapes (round, square, and rectangular).

Moreover, we are seeing a growing migration in the microelectronics industry toward through-silicon via (TSV) technology for 3-D wafer stacking. This technology requires significant reduction in substrate thickness and exponentially increases the complexity of handling for every subsequent processing step. The thinned substrate materials include silicon for advanced packaging as well as compound semiconductor (CS) materials including gallium arsenide (GaAs), gallium nitride (GaN), indium phosphide (InP), and silicon carbide (SiC) for high-power radio-frequency (RF) devices and light-emitting diodes (LEDs). The CS and III-V materials are extremely brittle and far more sensitive to both mechanical and thermal shock.  Film frames are commonly used to support silicon (Si) and CS materials. A device wafer can be mounted onto a film frame after backside processing but while it is still supported by its carrier, as in the Brewer Science® ZoneBOND™ process, or following separation (debonding) from the carrier, as in the thermal slide debonding process, for subsequent transport, cleaning, and packaging.

Issues with standard vacuum spin chucks

Process engineers often encounter a major hurdle with standard vacuum chucks that use a series of concentric circles and/or small-diameter perforated holes to supply vacuum through the spin chuck surface. These designs distribute the vacuum unevenly across the surface and cause dimples, deflection, and/or, in worst-case scenarios, cracking. Furthermore, all of these detrimental anomalies will lead to less-than-optimal film characteristics across the substrate. A film frame support structure will assist in handling these delicate films; however, any irregular chuck topography will detrimentally affect total thickness variation (TTV). Therefore, specialized spin chucks are recommended to safely contact thinned substrates without risk to delicate structures and subsequent film uniformity.

Alternative spin chuck designs

For thinned substrates (< 250 µm thick), we have developed a porous ceramic insert design that has a distinct advantage of completely supporting the backside of any given substrate dimension. The chuck distributes the vacuum equally through a porous surface and mitigates any potential deflection, eliminating detrimental effects to your substrate or coat quality. These chucks are design specific and available for a wide array of shapes and sizes.

ceramic insert chuck

The porous ceramic design can also be adapted for thinned substrates mounted to film frames. Mechanical clamps and a porous ceramic insert combine for spin processing thinned substrates (< 250 µm thick) that have been taped to frames. The ceramic insert ensures complete and uniform backside support, while it distributes the vacuum source across the taped surface. This design also utilizes vacuum O-rings and mechanical clamps for securing the outer film frame to the chuck assembly and maintaining positive lock.

film frame chuck

Although these chucks enable safe handling of ultrathinned substrates, they are exponentially heavier and create significantly more inertia than standard round vacuum chucks. To achieve adequate acceleration rates, these chucks can only be used on spin coaters with high-horsepower drive systems. All Brewer Science® Cee® spin coaters feature the industry’s highest-horsepower servo-motor indirect drive system and will allow the direct transfer of standard spin processing conditions. This system delivers the unique capability of combining porous ceramic chuck technology, existing high acceleration rates, and multiple spin-speed steps to fully optimize your thin-wafer processing application.

Lithography process simplification for reduced cost of ownership

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Cost of ownership plays an important role in lithography process materials and methods decisions. Process simplifications brought about by layer-to-layer synergy drive significant cost of ownership advantages for multilayer lithography systems such as the Brewer Science® OptiStack® system. Savings in mask engineering and manufacture are the greatest cost difference. Optical proximity correction (OPC) algorithms need only be determined once for all layers, rather than individually for each layer, which results in fewer mask corrections. Advanced devices with smaller critical dimensions benefit most from this system in that there are more layers at smaller critical dimensions, requiring greater mask design and production costs.

For the purpose of providing a cost of ownership estimate, we compared a process using the OptiStack® system on eight layers to a typical dyed resist process. Note that the OptiStack® system process would use the same OPC algorithm on all layers.  More layers utilizing the same system will result in greater savings. We assumed that 2500 wafers[1] would be printed from each mask; this is said to be a typical usage - ASIC masks may be imaged on as few as 500 wafers. Mask design and mask production are the significant cost components in any analysis of lithography process cost of ownership[2]. For a high-performance mask set with 90-nm design rules, individual binary chrome-on-glass masks can cost $100,000 to produce, and phase shift masks can cost as much as $124,000[3]. As a conservative estimate, the average mask cost was taken to be $70,000 because some layers can be printed using DUV tools and masks. Accounting for these and other costs, the OptiStack® system saves about $674 per wafer. The cost comparison is shown in Table I. “Other Optistack system costs” are caused by additional materials and processing.

Using this type of multilayer system is likely to bring even more benefits to the overall fab cost and efficiency. Other areas to be studied in future work are the impact of simplified inventory arising from the need for fewer custom materials by layer or device.

References

1. Harry J. Levinson, Principles of Lithography, The Society of Photo-Optical Instrumentation Engineers, 2005.

2. Vivek Bakshi, Ed., EUV Lithography, SPIE Press, Bellingham, WA, 2009.

3. B. Grenon and S. Hector, “Mask costs, a new look,” Proceedings of SPIE, vol. 6281, 2006, 62810H.

Supply chain flexibility for 3D device packaging

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3D supply chain

Limitations of Moore's Law

Ultimately, performance of computers and other electronic products will be limited by transistor size and density. Because the semiconductor industry has pushed to create ever-smaller features with photolithography, engineers have been able to shrink transistors far beyond original expectations to dramatically increase the density of transistors on a chip, thereby enabling the phenomenal leaps we have seen in the functionality and speed of electronics. However, the rate of performance improvements has become slower than originally predicted by Moore’s law because of the length of the connections between transistors and between individual semiconductor devices in components.

Increasing computing speed with through-silicon vias (TSVs)

Using through-silicon vias (TSVs) to directly interconnect semiconductor chips offers the promise of even greater functionality and faster computing speeds. Recent studies have indicated that computing speed may be increased by more than 10 times by using TSVs, and the associated decrease in inductive losses will reduce power consumption by more than 70%.

Implementation of TSV production requires the ability to handle and process ultrathin wafers as if they were at their full thickness. Most frequently, the full-thickness wafer is mounted on a rigid carrier using an adhesive that at later stages allows separation of the thin device wafer, which contains TSVs, from the carrier and removal of the adhesive. Although wafer-to-wafer bonding has been in use for some time for permanent bonding applications, and waxes have been used to bond wafers to carriers for thinning and subsequent removal, these processes have not been developed and optimized to allow further processing on the thinned wafer back side and permit separation from the carrier.

Supply chain options for 3D device packaging

Flexible options for temporary wafer bonding processes, with a variety of investment options, are available for 3DP applications. Device wafers can be mounted, demounted, and cleaned utilizing cost-effective equipment solutions. While mounted to carriers, device wafers may be thinned and may undergo backside processing as needed to create TSVs. Track-quality equipment performance enables scale testing of bonding, debonding, and cleaning processes. This flexibility, and the choice to select from a variety of options, creates a confidential pathway for completing thinned wafer processing feasibility work. Development time is reduced and the introduction of new 3DP applications to the market is accelerated.

For high-volume manufacturing (HVM) environments, Brewer Science has partnered with HVM equipment suppliers to qualify materials and processes for thin wafer handling needs. Customers can select an equipment supplier of their choice, one that can best meet their needs and provide the needed throughput and compatibility with their existing production environments. These suppliers offer equipment for mounting device wafers to carriers and then separating and cleaning the thinned wafers for final packaging.

Brewer Science technology provides customers flexibility for device development, process confirmation, and eventual scale to production.

Protecting key device features during wet-etch processing

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With the explosion in demand for devices that include features in the tens to hundreds of microns, wet-etching is seeing new relevance. Light-emitting diodes (LED), microfluidic devices, ink-jet printer heads, sensors, and many other devices are being mass produced in semiconductor-fab-like environments. However, these feature sizes often do not demand the precision, of plasma etching, nor can they tolerate the cost.

One challenging reality of wet etching is that the entire wafer is exposed to the etchant. To advance the use of such cost-effective batch processing, etch protection schemes must be employed. Brewer Science’s ProTEK® materials are spin-applied polymeric coatings engineered to withstand commonly used etchants, enabling myriad protection strategies.

Blanket Etch Protection

Blanket protection refers to coverage of an entire wafer surface and can even include wafer edge protection. Blanket protection is also discussed in a previous blog article describing its use in deep reactive ion etching (DRIE).

Patterned Etch Protection

Sometimes blanket protection is not needed. It is often desirable to etch specific areas on a wafer surface while protecting others. Photosensitive protective materials, such as ProTEK® PSB coating, address this need. An increasingly common example occurs in the manufacture of high-brightness LEDs (HB LEDs). To improve light extraction, the surface of the light-emitting material is roughened using a harsh wet-etching process. However, other elements of the device (e.g., metal pads) would be damaged during the etch.

Screen Shot 2012 01 16 at 3.16.34 PM

ProTEK® PSB coating can be pattern-exposed and developed to cover only these sensitive elements, and can be subsequently removed without damaging the device.

Conclusion

Processes utilizing the ProTEK® family of materials and processes enable surface etch protection, patterned etch protection, and edge protection. These materials can be used in combination to address a wide range of processing needs, providing lower-cost options to device manufacturers.

Planarization: Leveling extreme topography for microelectronics

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Fabrication of microelectronic devices increasingly involves the creation of high-aspect-ratio structures (those with large height or depth and narrow width, such as trenches, vias, columns, and mesas).  These structures provide isolation; serve as conduits for electrical, optical, or fluid signals; or enable pre-dicing before die singulation. New designs in semiconductor and MEMS devices are pushing the aspect ratios to the 10:1 range.  For semiconductors, these designs may take the form of trenches 600 nm deep and 60 nm wide. For MEMS, these may be vias 500 µm deep and 50 µm in diameter. After these structures are created, additional photolithographic processing of the wafers is necessary. The technology to create these high-aspect-ratio structures, however, has outpaced the ability of existing technologies to process photoresists over them.  This disparity has created a demand for materials that can level the surface of these processed wafers so that subsequent conventional photolithography processes can be used.

Many methods exist to planarize substrates, but three are compatible with a standard lithography track: the dry-etch-back, wet-develop-back, and expose-and-develop methods.

 

Dry-etch-back method

Dry etch back methodThe dry-etch-back method of planarizing is straightforward. Typically an organic film is coated on the wafer. This material must have self-leveling properties to minimize the difference in overburden between areas with high feature density and areas with low feature density. 

Overburden is the thickness of material extending beyond the top of the trenches. Self-leveling is the tendency of the material to flow or re-flow during processing to create a uniform, flat surface across the wafer.

Once the material is coated and baked, the wafer is placed in a dry-etch chamber and oxygen ashed to remove the overburden. 

The advantage to this method is that a wide range of materials can be used. Depending on the selection of the material, the methods for removing the fill include dry etching, wet etching (with solvent or developer), or thermal decomposition.

The disadvantage of this method is that it does require a dry-etching tool.  Also, during the dry-etch-back process, other organic films on the substrate may be damaged.

 

Wet-develop method

Wet-develop methodThe next method of planarizing a substrate is wet developing. This method is similar to the dry-etch-back process except that TMAH developer or a solvent is used to remove the overburden.  For many of our materials, we find that the etch rate of the overburden material is much faster than the etch rate of the material in the vias or trenches.  This difference reduces the iso-dense variance. 

An advantage of this method is that all the processing can be performed on a standard litho track.  Also, the film can be later removed by the same wet processing.  The disadvantage is that the ability to be removed in developer or solvent may limit downstream processing.  In some cases, the material can be cured after developing so that it is no longer soluble.  This, however, then limits later removal to dry etching only.

 

Expose-and-develop method

Expose-develop methodIn the expose-and-develop method, a photosensitive material with self-leveling properties is used.  The material is coated on the wafer and then baked. The wafer is then exposed by photolithography (the material is typically negative acting) to set the material in the vias or trenches. The overburden in the open areas is removed by either a TMAH developer or a solvent developer, depending on the planarizing material being used. After exposure, the material in the vias is normally removed by plasma etching.

Brewer Science offers many materials that can be used to level the surface of the substrate. Selecting the correct material depends on the scale of the structures (nanometer, micrometer, or millimeter), the aspect ratios, and the desired processing method.

Overcoming spin-coating challenges for square substrates

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Process application engineers often encounter a variety of complex challenges related to deposition by spin coating, as many variables affect the quality of the spin-applied coating. These variables have critical effects on the overall coating uniformity, coating thickness, and subsequent device yield. Some of the more influential variables that must be controlled precisely are spin speed, acceleration, and airflow/fume exhaust.

Typical spin-coating recipes involve dispensing a small puddle of fluid resin onto the center of a round substrate. This material spreads due to the radial centripetal acceleration force and evenly flows across the entire surface of the substrate. Final coating thickness and coating uniformity (measured as total thickness variation) are affected by final rotational speed, acceleration, ambient airflow (turbulence), and fume exhaust. Process engineers have utilized spin-coating techniques for decades, and they produce predictable results when standard round substrates are used.

Standard round substrates feature an inherent advantage in airflow dynamics compared to other exterior shapes in that they generally feature smooth, contoured (radial) edges and cause minimal disruption to the ambient air environment. This shape produces relatively uniform evaporation rates, as the fluid moves toward the radial edge during the spreading and subsequent drying steps. The resulting edge profile effect is very consistent and can be optimized through many standard process techniques.

Coating uniformity issues with square substratesNot all substrates are round, however. Square and rectangular shapes are commonly processed for a wide array of applications, including semiconductor photomasks, displays, and photovoltaic (PV) solar panels. These square and rectangular substrates create unique and complicated challenges for spin-coating applications through increased air turbulence. The leading edge of a square or rectangle causes significant turbulence when it contacts the internal spin bowl atmosphere, which leads to uneven evaporation of the film resin and anomalies in both thickness and uniformity of the coated film. Common film imperfections seen on square or rectangular substrates are often referred to as “edge buildup,” “fringing,” or corner “interference bands.”

Using a recessed spin chuck elegantly solves these problems by virtually eliminating the air disruption and resulting film non-uniformity. This design emulates a round substrate and removes the effect of the leading edge of the square or rectangle, thus dissipating the normal turbulence in the spin bowl atmosphere. These chucks virtually eliminate edge interference bands (corner fringing) and are custom-designed for each specific substrate dimension. Additional advantages of this design are its ability to auto-center and to provide both lateral and vacuum grip, as well as its ability to protect the back surface of the substrate and mitigate potential contamination.

Recessed spin chuckWhile recessed chucks have important advantages, one disadvantage is that they are magnitudes heavier and create considerably more inertia than that created by standard round substrates. This added weight has a negative impact on spin speed acceleration. Any reduction in spin speed acceleration toward the final spin velocity can have dramatic effects on the final properties of the coated film. Because the resin begins to dry during the initial part of the spin cycle, it is important to accurately and aggressively control acceleration rates. In many cases, up to 50% of the solvents in the resin will be lost to evaporation in the first few seconds. Many process engineers utilize “snap” spin recipe techniques to aggressively cast the material from the center to edge in less than 3 seconds with maximum acceleration (5,000-20,000 rpm/s), followed by a much slower (< 500 rpm) drying step.

Unfortunately, many standard spin coaters lack the necessary horsepower or torque in their spindle drives to directly transfer spin recipe parameters (speed and acceleration) from standard-diameter substrates to recessed chuck applications. The Brewer Science® Cee® line of spin coaters and developers feature indirect drive systems with the industry’s highest horsepower (servo motor) and will allow the direct transfer of standard spin process conditions, even when using the heavier recessed chucks. This feature enables the unique capability of combining recessed chuck technology with existing high acceleration rates and multiple spin speed steps to virtually eliminate edge effect issues that can arise with irregular substrates.

Thermally curable middle layer for 193-nm trilayer resist process

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New lithographic compositions, for use as middle layers in trilayer processes  resist processes can be applied as very thin films with a very thin layer of photoresist being applied to the top of the middle layer. Thus, the underlying bottom anti-reflective coating is still protected even though the overall stack (i.e., anti-reflective coating plus middle layer plus photoresist) is still thin compared to prior art stacks.


Present Methodology
In order to store ever-increasing amounts of information on a substrate area, the microchip industry continues to move to shorter and shorter wavelengths of light for resist exposures. This trend towards decreasing linewidths leads to high aspect ratio lines, with the thin, tall lines tending to fall over during resist development/rinse steps. For 193-nm exposures, the microchip industry typically uses roughly 270-350 nm of resist on 32-80 nm of bottom anti-reflective coating--so-called unilayer processing. For trilayer applications, photoresist thicknesses (.about.150-200 nm) are much less than for unilayer applications, resulting in low aspect ratio lines. The trilayer bottom anti-reflective coating instead is 300-700 nm thick, and the middle layer is 30-215 (preferably 30-60) nm thick. The advantages of the trilayer resist processing include:

  • (a) reduced resist aspect ratios;
  • (b) the ability to use conventional or ultra-thin 193-nm photoresists rather than silicon-containing and hydrophobic (bilayer) resists;
  • (c) minimized interaction of resist with the substrate;
  • (d) optimum thickness control for the imaging, masking, and anti-reflective layer; and
  • (e) improved depth-of-focus (DOF) since the trilayer bottom anti-reflective coatings are designed to be highly planarizing.

The key to trilayer imaging is a robust middle layer offering facile spin-applied processing, acceptable bottom anti-reflective coating/resist adhesion, excellent imageability, and outstanding etch selectivities to both bottom anti-reflective coating and resist. The middle layer must etch much slower than the bottom anti-reflective coating in an oxygen plasma and preferably faster than the photoresist in a fluorinated gas plasma. Prior approaches to the middle layer problem include the use of spin-on-glass, which requires careful attention to surface acidity in order to achieve acceptable adhesive properties.

New Options
The present invention is broadly concerned with new lithographic compositions and methods of using those compositions as middle or protective layers during circuit manufacturing.

In more detail, the compositions comprise a polymer or compound dispersed or dissolved in a solvent system. In one scenario, that polymer is an organo-silicon polymer, preferably including recurring monomers having the formula.

Additional information about Thermally curable middle layer for 193-nm trilayer resist process can be learned from United States Patent 7,507,783, Thermally curable middle layer comprising polyhedral oligomeric silsesouioxanes for 193-nm trilayer resist processes.

High-k metal gate (HKMG) technology for CMOS devices

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High-k metal gate (HKMG) technology has become one of the front-runners for the next generation of CMOS devices. This new technology incorporates a high-k dielectric, which reduces leakage and improves the dielectric constant. To help with fermi-level pinning and to allow the gate to be adjusted to low threshold voltages, a metal gate is used instead of a polysilicon gate. By combining the metal gate and low-k dielectric, HKMG technology reduces gate leakage, thereby increasing the transistor capacitance and allowing chips to function with reduced power needs.

The two common process flows to pattern the HKMG stack are gate-first and gate-last. The gate-first HKMG process is very sensitive, as the capping metal that must be patterned is very thin. Photoresists do not adhere well to the metal layers, which is made worse by the wet chemistries used to etch the capping metal.

Brewer Science® developer-soluble bottom anti-reflective coatings (DBARCs) are an enabling technology used to pattern the metal capping layers in the gate-first HKMG process. DBARCs protect the substrate by patterning with the photoresist and eliminating the use of reactive ion etching (RIE). Additional value is found in the crosslinking ability of a DBARC, which increases the substrate adhesion, allowing the wet-etch process to transfer the pattern through the capping metal.

Controlling the spin bowl environment to optimize spin coat quality

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A variety of factors can affect the coat quality when spin processing. This article will focus on the role that the bowl environment, and in particlar the ability to control the fume exhaust, has on this process.

The drying rate of the resin fluid during the spin process is defined by the nature of the fluid itself (volatility of the solvent systems used) as well as by the air surrounding the substrate during the spin process. Just as a damp cloth will dry faster on a breezy dry day than during damp weather, the resin will dry depending on the ambient conditions around it. It is well known that such factors as air temperature and humidity play a large role in determining coated film properties. It is also veryFume Exhaust important that the airflow and associated turbulence above the substrate itself be minimized, or at least held constant, during the spin process.

To be able to control this environment, there are some destinct advantages to using a "closed bowl" spin coater. While an airtight environment is not required, the exhaust lid should allow only minimal exhaust during the spin process. Combining with an exhaust port, preferably located beneath the spin chuck, the exhaust lid becomes part of a system to minimize unwanted random turbulence. The two distinct advantages to this system are:
1. slowed drying of the fluid resin
2. minimized susceptibility to ambient humidity variations

The slower rate of drying offers the advantage of increased film thickness uniformity across the coated substrates. Because the fluid dries as it moves toward the edge of the substrate during the spin process, radial thickness non-uniformities may occur since the fluid viscosity changes with distance from the center of the substrate. By slowing the rate of drying, it is possible for the viscosity to remain more constant across the substrate.

ExhaustDrying rate and hence final film thickness is also affected by ambient humidity. Variations of only a few percent relative humidity can result in large changes in film thickness. By spinning in a closed bowl the vapors of the solvents in the resin itself are retained in the bowl environment and tend to overshadow the affects of minor humidity variations. At the end of the spin process, when the lid is lifted to remove the substrate, full exhaust is maintained to contain and remove solvent vapors.

Another advantage to this "closed bowl" design is the reduced susceptibility to variations in air flow around the spinning substrate. In a typical clean room, there is a constant downward flow of air at about 100 feet per minute (30m/min). Various factors affect the local properties of this air flow. Turbulence and eddy currents are common results of this high degree of air flow. Minor changes in the nature of the environment can create drastic alteration in the downward flow of air. By closing the bowl with a smooth lid surface, variations and turbulence caused by the presence of operators and other equipment are eliminated from the spin process.

Maintaining spin coat uniformity is critical to the creation of micro devices and using a controlled, closed bowl environment can be a key element to achieving coat uniformity success.

Protecting front-side circuitry during backside DRIE processing

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The demand for microelectromechanical systems (MEMS) requiring tall structure designs, as well as the increased density and performance expectations from the IC industry, are driving the need to utilize deep reactive ion etching (DRIE) in creating deep anisotropic etches of silicon for MEMS and semiconductor device applications. Vast yield hits are frequently the outcome of this process, where it is necessary to subject the front side of the substrate containing fragile, etch-sensitive circuitry to direct contact against the interior chuck of the etch chamber.

DRIE Advantages
Backside DRIE processes offer significant advantages over silicon wet-etch processes because of their ability to create very deep anisotropic vias. This ability allows manufacturers to maintain their target feature sizes during the entire etch. The DRIE process is frequently performed on substrates that have been previously subjected to costly processing steps necessary to create intricate device circuitry. These sensitive device features can be easily damaged as a result of undergoing the intense bombardment of plasma to the backside of the substrate. Additional benefits of DRIE processes include an increase in computational capacity utilizing flexible interconnects, increased electrical performance through shorter wire runs, and lower costs than existing CMOS techniques.

DRIE process

DRIE Applications
The backside DRIE process is used in MEMS to create devices such as microfluidics (ink-jet heads, BioMEMS), silicon microphones, pressure sensors, inertial sensors (gyroscopes, accelerometers), and other sensing and actuation devices. Increasingly, the DRIE process is used in CMOS to create through-wafer interconnects for packaging, chip stacking, and system-in-package (SiP) devices.

DRIE Solutions

Providing maximum protection for fragile, etch-sensitive circuitry placed in direct contact with the interior chuck of the etch chamber is critical. Photoresists have been used but they do not provide scratch resistance and are difficult to remove. Using a spin-applied polymeric coating that offers durability and longevity against the harsh, grueling backside DRIE processes is a viable solution.

Enabling DRIE Processes
A multitude of applications and industrial processes utilize backside DRIE processes. No longer is this type of etching process limited to MEMS devices such as gyroscopes, accelerometers, inertial sensors, or other membrane applications in sensing and actuation. DRIE processes are enabling the creation of CMOS processes where the MEMS devices can co-exist with integrated circuitry.