The gate-structure fabrication is a critical step in the development of an integrated circuit (IC) in that the purity of material and the dimensions of the structure determine the performance of the IC. The gate is formed from polysilicon-film and then doped with phosphorus by ion-implantation or chemical-doping. The gate-structure is patterned by applying an ARC® layer then the photoresist layer. Following photoresist exposure and development the polysilicon-film is dry-etched.
The ARC layer is a necessary component to the formation of the gate-structure in that critical dimension control of this structure determines the performance of the IC. With the ARC layer controlling reflectivity, standing waves and reflective notching, the structure dimensions are uniform. The planarization of the topography across the device aids in creating a more consistent substrate for the photoresist to cover. Therefore, the photoresist thickness remains relatively consistent.
Below is an example of a gate electrode fabrication utilitaring an ARC layer under the photoresist layer.
Diagram 1. After the formation of the P and N wells, a layer of Polysilicon is deposited and then heavily doped with Phosphorus.
Diagram 2. An ARC layer is applied to the substrate prior to the photoresist.
Diagram 3. The photoresist layer is then exposed and developed. The resulting photoresist feature is then transferred into the ARC layer by reactive ion etching (RIE). The combined photoresist/ARC etch mask is then transferred into the polysilicon by an anisotropic RIE etch to define the gate length. The photoresist and ARC layers are then stripped off of the substrate.
