MEMS, Sensors & Displays

MEMS image

Materials and processes that enable MEMS device manufacturing

Brewer Science develops and manufactures a broad range of organic materials and provides process integration that enables the fabrication of MEMS devices.

Brewer Science® processes have been successfully applied in applications typically used in MEMS fabrication, including:

Micromachining

Micromachining is divided into two categories: surface and bulk. In surface micro-machining, layers are added to the substrate and are patterned to create structures. Bulk micromachining uses various techniques to remove pieces of the substrate to create a pattern in the substrate. Most MEMS devices are created using both types of micromachining.

Surface Micromachining
Surface micromachining entails growing, depositing, or coating thin films on a substrate and then patterning the films with a dry or wet etching process. Surface micromachining provides finer, more detailed structures in comparison to bulk micromachining.

To enable high-quality surface micromachining, Brewer Science offers anti-reflective coatings, sacrificial layers, planarizing coatings, and optical coatings.

Brewer Science® anti-reflective coatings improve the photolithographic process, enabling fine resolution of photoresist features.

Brewer Science® sacrificial layer materials allow the patterned deposition of metals, oxides, and inorganics. Typically the sacrificial layer is placed under a photoresist so that the photoresist can be removed after deposition.

As structures on the substrate become more three-dimensional (3-D), photoresist uniformity over the structures becomes more difficult. Brewer Science® leveling materials fill in the structures to create a flat surface for the photoresist. Once the photoresist has accomplished its task, it and the leveling material are normally removed.

Brewer Science® optical coatings provide transparent films that are spin-applied and offer either high or low refractive indices.

Materials:
  • ARC® bottom anti-reflective coatings
  • ARC® Anti-Reflective Coatings

    Litho profiles with and without the use of a BARC

    Brewer Science® ARC® anti-reflective coatings improve the photolithographic process, enabling fine resolution of photoresist features.

    Brewer Science is the expert in manufacturing and implementing anti-reflective coatings for the semiconductor industry. Our line of products stretches across the whole spectrum of wavelengths and is the most comprehensive product line-up in the industry.

    About ARC® coatings

    Bottom anti-reflective coatings (ARC®) are polymer based liquid chemistries that have three primary functions in the creation of a semiconductor.

    1. The light absorbing chemistry controls light as it passes through the photoresist during the photolithography stage of chip manufacturing. The result is a dampening of reflected light on the surfaces and inside the material (destructive interference).
    2. Reduces or eliminates reflective notching and standing waves and doesn't need additional adhesion promoter.
    3. The liquid chemistry typically flattens surface topography.

    Spin coating BARC can increase depth of focus and reduce reflective notching.

    By using anti-reflective coatings, semiconductor chip manufacturers have been able to push their process windows to create the smaller features that today's consumers have come to expect.

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  • Level™ M10 planarizing material
  • Level® M10 Planarizing Material

    Level™ M10 planarizing coating can be used to  planarize high-aspect-ratio structures Level® M10 self-leveling material provides a planar surface when coated over high-aspect-ratio structures. This spin-applied coating offers the following benefits:

    • Facilitates lithography over severe topography
    • Provides a stable surface for application of resists and other thin films
    • Transfers planar surface to underlying organic films by dry etching

    Other benefits include:

    • Spin-applied from a coating solution with high solids to limit shrinkage and promote good filling properties
    • Thermally reflowed prior to curing to improve surface planarity
    • Utilizes fast UV curing
    • Provides stable surface for application of resists and other thin films
    • Removable by plasma ashing

    Level® M10 planarizing coating is used to planarize high-aspect-ratio structures

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Bulk Micromachining
Bulk micromachining is a process of removing pieces of the substrate. This process can be done using a wet process (alkaline or acidic etching) or it can be done using gas particles to “sandblast” the surface (deep reactive ion etching, DRIE). In wet processes, areas of the wafer are masked to prevent the etchants from reaching the surface. These areas will remain intact after the wet etch. Typical masking materials are inorganic films or spin-applied organics. The inorganic films, such as silicon nitride or silicon oxide, are chemically vapor deposited.

Organic films, such as Brewer Science® ProTEK® coatings, are spin-applied.  These films can be used as either blanket coatings to protect one side of the wafer or are exposed to UV light to pattern them.

Materials:
  • ProTEK® B3 coatings for alkaline etching
  • ProTEK® B3 Coatings Alkaline protective coating

    ProTEK<sup>®</sup> B3 coating

    ProTEK® B3 thin films are spin-applied polymeric coating systems that provide temporary wet-etch protection for CMOS MEMS circuitry during alkaline or acid etches. ProTEK® B materials offer protection from alkaline solutions such as KOH and TMAH for extended bath etches.

    Download Datasheet

    With ProTEK® B3, you can:
    • Protect delicate front-side circuitry during back-side bulk micromachining
    • Increase yield by minimizing front side damage caused by alkaline etch solution punch through during wet etch
    • Improve throughput by reducing labor and process time associated with mechanical clamps and increasing the number of wafers per etch bath
    Apply ProTEK® B3 coating instead of mechanical clamps to:
    • Protect CMOS circuitry or MEMS structures
    • Create SiN membranes last
    • Create through-silicon vias (TSVs)
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  • ProTEK® SR coating for dry etching
  • ProTEK® SR Coatings Scratch-resistant coating

    ProTEK® SR coating is a spin-applied polymeric coating designed to provide maximum protection for fragile, etch-sensitive circuitry placed in direct contact against the interior chuck of the etch chamber. ProTEK® SR coating offers durability and longevity against harsh backside DRIE processes typically utilized by the microelectromechanical systems (MEMS) and integrated circuit (IC) industries.

    ProTEK® SR coating offers the following features:

    • Durable polymer coating protects delicate front-side circuitry during backside DRIE etching.
    • High film hardness (9H pencil) resists scratching.
    • High glass transition temperature (117°C) assures ProTEK® SR film will not stick to DRIE chuck.
    • Low outgassing in a vacuum assures no contamination of DRIE chamber or process.
    • Low film ion levels prevent contamination of wafers, tools, and handling equipment.
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Surface Energy Modification

In constructing many of today’s MEMS devices, it is necessary to modify the surface of the substrate to improve adhesion of additional coatings or to prevent substances from attaching to the substrate.

Brewer Science offers coatings that change the surface energy of the substrate to enhance the desired surface properties. The coatings can provide high, medium, or low surface energies to attract or repel other chemistries. APX-K1 material is a spin-on coating that produces films nanometers thick, offers high surface energy, and attracts similar high-surface-energy coatings.

Brewer Science® Theta™ coatings offer low surface energy to repel water, inks, and other materials. These coatings come in versions that produce films with a range of thicknesses, from monolayers that are a few nanometers thick to films that are microns in thickness.

Materials:
  • APX-K1 coating
  • Theta™ M10 coatings

Leveling Topography

Bulk micromachining and surface micromachining are used to create 3-D structures. As semiconductor devices have advanced, the aspect ratio of these structures has increased from a 1:1 height-to-width ratio to a 10:1 ratio. The processes used to make these structures, however, can severely damage microelectronic circuitry that already exists on the wafer.

In many cases, it is easier to create the high-aspect-ratio features before starting the fabrication of the microelectronic circuits. The disadvantage of this alternative is that spin-coating additional materials is difficult once the 3-D structures have been created. Having the ability to temporarily fill in the structures and return the substrate’s surface to a flat profile allows the use of existing photolithography tools, processes, and materials. This capability, in turn, broadens the design latitude that an engineer has in crafting a device.

Many methods exist for planarizing the substrate. Three methods that can be used with lithography tracks are:

  • Dry etch back
  • Dry Etch Back

    The advantage of this method is that a wide range of materials can be used. Depending on the material selected, methods for removing the fill include dry etching, wet etching (with solvent or developer), or thermal decomposition.

    The disavantage of dry etching is that it does require a dry-etch tool. Also, during the dry-etch-back process, other organic films on the substrate could be damaged.

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  • Expose and develop
  • Expose and Develop

    The last method for leveling topography is expose and develop. In this method, a photosensitive material that has self-leveling properties is used. The material is coated on the wafer and baked. The wafer is then exposed by photolithography (the material is typically negative acting) to set the material in the vias or trenches. The overburden in the open areas is removed by either a TMAH developer or a solvent developer, depending on the planarizing material being used. After exposure, the material in the vias is normally removed by plasma etching.

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  • Wet develop back
  • Wet Develop Back

    The wet-develop method is similar to the dry-etch-back process except that either TMAH developer or a solvent is used to remove the overburden. For many of our materials, we find that the etch rate of the overburden is much faster than the etch rate of the material in the vias or trenches. This characteristic reduces the iso-dense variance.

    An advantage of the wet-develop method is that all the processing can be performed on a standard lithography track. Also, the film can be removed later by the same wet processing. The disadvantage is that the the film’s ability to be removed in developer or solvent may limit downstream processing. In some cases, the material can be cured after developing so that it is no longer soluble. However, curing limits the removal method to dry etch only.

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Thin Wafer Handling

Wafer-level packaging (WLP) is commonly used for packaging of MEMS and LED devices as it offers advantages in cost, yield, and reliability. In a WLP scheme, MEMS structures or LED die are encapsulated between bonded wafers, one of which has cavities that are fabricated most commonly by bulk micromachining.

The thinned silicon wafers are fragile and require a temporary rigid support that allows the wafer to be successfully processed for stacking. When finished, the thin processed wafer must be separated from the rigid support using a simple, cost-effective process, without resulting in damage.

The bonding materials used to attach the device wafer to the rigid support, or carrier, must meet very stringent requirements. They must survive extreme temperatures, harsh corrosive and solvent chemistries, and mechanical stresses created by thermal excursions. They must permit separation (debonding) of the very delicate wafer from the rigid carrier, and leave no residue after debonding and cleaning.

Materials:
  • WaferBOND® HT-10.10 thermal release material
  • WaferBOND® HT-10.10 Temporary bonding material

    WaferBOND® HT-10.10 temporary bonding material enables back-end-of-line processing of ultrathin wafers with standard semiconductor equipment

    With WaferBOND® HT materials, you can:
    • Process ultrathin wafers in temperatures up to 220°C
    • Protect the wafer edge from chipping
    • Protect circuitry from harsh chemical etchants
    • Provide a void-free interface for a smooth surface on the final thinned wafer
    Debonding with the WaferBOND® HT System

    The WaferBOND® HT coating is mechanically debonded by heating the processed wafer until the carrier can be slid from the ultrathin wafer.

    The WaferBOND® HT system supports high-throughput processes by enabling short debonding times. Debonding time is < 5 minutes.

    Stripping Process for WaferBOND® HT Materials
    • Residue-free vias with Brewer Science® WaferBOND® Remover
    • Reduced defects compared to existing technology

    Stripping Process for WaferBOND<sup>®</sup> HT Materials Stripping Process
    Vias: 0.7 µm wide, 0.7 µm deep

    Improve throughput of high-temperature ultrathin-wafer processing

    Excellent void-free bonding and high-temperature stability delivered by the WaferBOND® HT product series increases yields and provides greater process latitude.

    Additional benefits:
    • Excellent uniformity
    • Low defects
    • High throughput
    • Ability to be applied and removed with EVG® bonding and debonding equipment platform specifically designed to work with WaferBOND® HT materials.
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  • WaferBOND® CR-200 chemical release material
  • WaferBOND® CR-200 Temporary bonding material

    WaferBOND® CR-200 temporary bonding material enables back-end-of-line (BEOL) processing of ultrathin wafers with standard semiconductor equipment.

    WaferBOND® CR-200 material enables:

    • Processing of ultrathin wafers using standard lithographic, passivation, and metallization techniques and tooling
    • Creation of interconnects before or after thinning
    • Preservation of delicate structures on III-V wafers through low-stress demounting
    WaferBOND® CR-200 material is used for:
    • Wafer thinning
    • Thinned wafer processing
    • Interconnect formation
    • Low-stress demounting
    WaferBOND® CR-200 properties:
    • Low-viscosity solution in solvent to provide planarization during spinning
    • Spin-applied coatings 10 to 27 µm thick
    • Thermal stability to 220ºC in bonded wafer pair state
    • Resistance to acids, bases, and most solvents
    • Transparent coatings under visible and infrared (IR) light for either optical or IR backside alignment
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