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Planarization: Leveling extreme topography for microelectronics

Fabrication of microelectronic devices increasingly involves the creation of high-aspect-ratio structures (those with large height or depth and narrow width, such as trenches, vias, columns, and mesas).  These structures provide isolation; serve as conduits for electrical, optical, or fluid signals; or enable pre-dicing before die singulation. New designs in semiconductor and MEMS devices are pushing…

  MEMS, Lithography, planarization Click Here to Read More

Protecting front-side circuitry during backside DRIE processing

The demand for microelectromechanical systems (MEMS) requiring tall structure designs, as well as the increased density and performance expectations from the IC industry, are driving the need to utilize deep reactive ion etching (DRIE) in creating deep anisotropic etches of silicon for MEMS and semiconductor device applications. Vast yield hits are frequently the outcome of…

  Lithography, scratch-resistant, DRIE, MEMS, etching, CMOS Click Here to Read More
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