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SEMICON China 2021

SEMICON China connects you to the world’s fastest-growing and most dynamic microelectronics market, and gives you the platform to showcase your products, technologies, and brand in front of the most qualified audience of industry professionals in China. SEMICON China will be held on March 17-19, 2021 in Shanghai, China, (and virtual) in conjunction with CSTIC…

  Events, Multilayer lithography, spin on carbon, high temperature, planarization, SC1 resistance Click Here to Read More

CSTIC (China Semiconductor Technology International Conference)

CSTIC 2021 is one of the largest and the most comprehensive annual semiconductor technology conferences in China and Asia since 2000. Organized by SEMI, IMEC and IEEE-EDS, co-organized by IMECAS. CSTIC 2021 will be held on March 14-15, 2021 in Shanghai, China, in conjunction with SEMICON China 2021. Virtual conference will be held on March…

  planarization, SC1 resistance, Events, Multilayer lithography, spin on carbon, high temperature Click Here to Read More

Planarization Innovations Help Semiconductors Go Even Smaller and More Complex

Imagine you’ve decided to undertake a home improvement project; you’re going to lay tile in the downstairs powder room. To begin, you remove the old vinyl flooring. Underneath are clumps and channels of dried adhesive atop a concrete slab foundation that looks like a miniature lunar landscape. In order to ensure your tiling project has…

  semiconductors, planarization Click Here to Read More

Planarization: Leveling extreme topography for microelectronics

Fabrication of microelectronic devices increasingly involves the creation of high-aspect-ratio structures (those with large height or depth and narrow width, such as trenches, vias, columns, and mesas).  These structures provide isolation; serve as conduits for electrical, optical, or fluid signals; or enable pre-dicing before die singulation. New designs in semiconductor and MEMS devices are pushing…

  MEMS, Lithography, planarization Click Here to Read More

Processing wafers with high-topography 3-D structures

Over the past decade, Brewer Science has developed and published various methods of creating a planar surface over three-dimensional (3-D) structures. Sharing these results invariably leads to a potential customer asking, “Can you fill the holes in my substrate that are x in size?” The short answer to the question is “Yes, we can.” Filling…

  Wafer-Level packaging, planarization, TSV Click Here to Read More
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