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The device you are using right now—whether it be a phone, tablet or even a computer—is smaller than its predecessors, yet its capabilities are far greater than ever before. With the challenge to produce microchips on the smallest scale possible, manufacturers must devise a solution to protect fragile integrated circuits, while dissipating heat and increasing…
Click Here to Read MoreUse of temporary bonding/debonding as part of thin wafer handling processes is rapidly increasing. Users must determine which temporary bonding/debonding method is appropriate for a specific application. Some of the technologies that have been developed are chemical release, thermal slide separation, and ZoneBOND® debonding. The chemical release process requires very little force to release the…
Click Here to Read MoreAlice Guerrero, Senior Applications Engineer in Wafer-Level Packaging at Brewer Science, and Koen Kennes, Research and Development Engineer at imec, contributed to Chip Scale Review with a discussion of the fundamentals of laser debonding and the advantages it has for 2D and 3D heterogeneous integration. Brewer Science and imec have several different products and programs…
Click Here to Read More“Just the tip of the iceberg.” What a great saying. It means what we can see pales in comparison to what we can’t. In the world of technology, people often marvel at the end product but rarely consider the extremely important advances and transitional processes that make it all possible. As smaller chip sizes and…
Click Here to Read MoreWhat makes it possible for our smartphones, tablets, gaming systems, networking devices, and everyday electronics to operate at faster speeds, process more information, and continue to shrink in size? Until now, the answer has included a number of advanced technologies and processes that have allowed the microelectronics industry to double the number of circuits in…
Click Here to Read MoreIn addition to precisely controlling application of the materials that enable wafer bonding, a solvent-enriched sealed spin chamber contributes to process integrity. One of the most critical variables in achieving optimal uniformities at the desired target thickness is airflow dynamics. Ideal conditions are created in a sealed chamber with a prewet solvent nozzle, a backside…
Click Here to Read MoreThe microelectronics industry is rapidly migrating to fabricating 3-D wafer stacking interconnects using through-silicon via (TSV) technology. Major market segments seeking to benefit from TSV technology include advanced packaging for memory/logic, light-emitting diodes (LEDs), and compound semiconductor (III-V) high-power radio-frequency (RF) devices. In this cutting-edge technology, fragile device substrates are bonded to carrier substrates with…
Click Here to Read MoreThin-wafer processing trends Several spin-coating process applications require the ability to uniformly coat, develop, and/or rinse (clean) thinned and fragile substrates. Safely handling these fragile materials is paramount and requires specially designed spin chucks and thin-wafer handling techniques. The substrates are made of a wide array of materials, and some of the more popular ones…
Click Here to Read MoreThermal slide debonding represents the next significant advancement in obtaining high-yield thin wafer results. Initial detection of anomalies and cracks usually occurs during debonding; however, many causes for this damage originate during upstream bonding material coating, curing, bonding, and thinning processes. Moreover, only thermal separation tools that are highly precise and highly accurate will consistently…
Click Here to Read MoreIn recognition of its progress with temporary bonding and thin wafer handling, Brewer Science was featured in the November/December issue of Chip Scale Review. The feature discusses the company’s use of wafer-level packaging (WLP) technologies in semiconductor segments, including fan-out WLP (FOWLP); fan-in wafer-level chip-scale package (FI-WLCSP); 3-D FOWLP; 2.5-D integration with interposer technology; and…
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